来源：http://www.fe.infn.it/~cotta/ILC/EUDET/EUDRB_MIMOSTAR2_Jan07/ProjectFiles/CypressUSB_Firmware_Driver/EUDRB_LOOPBACK/EUDRBLoopBack.LST
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 1
C51 COMPILER V7.07, COMPILATION OF MODULE EUDRBLOOPBACK
OBJECT MODULE PLACED IN EUDRBLoopBack.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE EUDRBLoopBack.c DEBUG OBJECTEXTEND
stmt level source
1 //-----------------------------------------------------------------------------
2 // File: EUDRBSpecific.c
3 // Contents: Hooks required to implement USB peripheral function.
4
5 //-----------------------------------------------------------------------------
6 // Copyright 2003, Cypress Semiconductor Corporation
7 // EUDRB Customization: INFN Ferrara - Servizio Elettronico - Angelo Cotta Ramusino - last mod: 22/08/2006
8 //-----------------------------------------------------------------------------
9 #pragma NOIV // Do not generate interrupt vectors
10
11 #include "fx2.h"
12 #include "fx2regs.h"
13 #include "syncdly.h" // SYNCDELAY macro
14
15 extern BOOL GotSUD; // Received setup data flag
16 extern BOOL Sleep;
17 extern BOOL Rwuen;
18 extern BOOL Selfpwr;
19
20 BYTE Configuration; // Current configuration
21 BYTE AlternateSetting; // Alternate settings
22
23 #define VR_NAKALL_ON 0xD0
24 #define VR_NAKALL_OFF 0xD1
25
26 //-----------------------------------------------------------------------------
27 // Task Dispatcher hooks
28 // The following hooks are called by the task dispatcher.
29 //-----------------------------------------------------------------------------
30
31 void TD_Init(void) // Called once at startup
32 {
33 1 int delaycount = 500; // risulta in una durata del segnale di reset di circa 412us verificati con sco
-pe
34 1
35 1 // set the CPU clock to 48MHz
36 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
37 1
38 1 // set the slave FIFO interface to 48MHz
39 1 IFCONFIG = 0xCB; // usa IFCLK interno 48MHz
40 1 // usa slave FIFO asynchronous interface
41 1 // 22/08/2006 ACR note: OK renumerates and lets the loopback work
42 1 // Registers which require a synchronization delay, see section 15.14
43 1 // FIFORESET FIFOPINPOLAR
44 1 // INPKTEND OUTPKTEND
45 1 // EPxBCH:L REVCTL
46 1 // GPIFTCB3 GPIFTCB2
47 1 // GPIFTCB1 GPIFTCB0
48 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
49 1 // EPxFIFOCFG EPxGPIFFLGSEL
50 1 // PINFLAGSxx EPxFIFOIRQ
51 1 // EPxFIFOIE GPIFIRQ
52 1 // GPIFIE GPIFADRH:L
53 1 // UDMACRCH:L EPxGPIFTRIG
54 1 // GPIFTRIG
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 2
55 1
56 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
57 1 // ...these have been replaced by GPIFTC[B3:B0] registers
58 1
59 1 // default: all endpoints have their VALID bit set
60 1 // default: TYPE1 = 1 and TYPE0 = 0 --> BULK
61 1 // default: EP2 and EP4 DIR bits are 0 (OUT direction)
62 1 // default: EP6 and EP8 DIR bits are 1 (IN direction)
63 1 // default: EP2, EP4, EP6, and EP8 are double buffered
64 1
65 1 /*
66 1 // 22/08/2006 ACR note: BEGIN this code stops the loopback. Do we need it?
67 1 REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1:
68 1 // REVCTL.1 ( DYN_OUT ) : 1 = disable autoarming on 0 to 1 transition of AUTOOUT
69 1 // REVCTL.0 ( ENH_PKT ) : 1 = enable enhanched packet endling
70 1 SYNCDELAY;
71 1 // 22/08/2006 ACR note: END this code stops the loopback. Do we need it?
72 1 */
73 1
74 1 // we are just using the default values, yes this is not necessary...
75 1 EP1OUTCFG = 0xA0;
76 1 EP1INCFG = 0xA0;
77 1 SYNCDELAY; // see TRM section 15.14
78 1
79 1 // 22/08/2006 ACR mod: make endpoint 2 an IN EndPoint
80 1 EP2CFG = 0xE2; // 22/08/2006 ACR mod: EP2 valid for IN packets, buffer size of 512 bytes, ONLY 2x bu
-ffered option available for endpoint4
81 1 SYNCDELAY;
82 1
83 1 // 22/08/2006 ACR mod: make endpoint 6 an OUT EndPoint
84 1 EP6CFG = 0xA2; // 22/08/2006 ACR mod: EP6 valid for OUT packets, buffer size of 512 bytes, ONLY 2x b
-uffered option available for endpoint4
85 1 SYNCDELAY;
86 1
87 1 // 21/08/2006 ACR mod: make endpoint 4 an IN EndPoint
88 1 // EP4CFG = 0xA2; // EP4 valido per OUT packets, for 512 byte packets, ONLY 2x buffered option availa
-ble for endpoint4
89 1 // SYNCDELAY;
90 1 EP4CFG = 0xE2; // 21/08/2006 ACR mod: EP4 valid for IN packets, buffer size of 512 bytes, ONLY 2x bu
-ffered option available for endpoint4
91 1 SYNCDELAY;
92 1
93 1 // 21/08/2006 ACR mod: make endpoint 8 an OUT EndPoint
94 1 // EP8CFG = 0xE2; // EP8 valido per IN packets, for 512 byte packets, ONLY 2x buffered option availa
-ble for endpoint8
95 1 // SYNCDELAY;
96 1 EP8CFG = 0xA2; // 21/08/2006 ACR mod: EP8 valido per OUT packets, buffer size of 512 bytes, ONLY 2x
-buffered option available for endpoint8
97 1 SYNCDELAY;
98 1
99 1 // 22/08/2006 ACR Begin: reset all FIFOs
100 1 FIFORESET = 0x80; // NAK per tutti i pacchetti
101 1 SYNCDELAY;
102 1 FIFORESET = 0x02; // resetta FIFO per endpoint2
103 1 SYNCDELAY;
104 1 FIFORESET = 0x04; // resetta FIFO per endpoint4
105 1 SYNCDELAY;
106 1 FIFORESET = 0x06; // resetta FIFO per endpoint6
107 1 SYNCDELAY;
108 1 FIFORESET = 0x08; // resetta FIFO per endpoint8
109 1 SYNCDELAY;
110 1 FIFORESET = 0x00; // fine del NAK-ing a tutti i pacchetti
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 3
111 1 SYNCDELAY;
112 1 // 22/08/2006 ACR End: reset all FIFOs
113 1
114 1
115 1 // 22/08/2006 ACR mod BEGIN: this section belonged (except with different OUT endpoints) to the bulkloop e
-xample. Let's keep it for now
116 1 // out endpoints do not come up armed
117 1 // since the defaults are double buffered we must write dummy byte counts twice
118 1 EP6BCL = 0x80; // arm EP6OUT by writing byte count w/skip.
119 1 SYNCDELAY;
120 1 EP6BCL = 0x80;
121 1 SYNCDELAY;
122 1 EP8BCL = 0x80; // arm EP8OUT by writing byte count w/skip.
123 1 SYNCDELAY;
124 1 EP8BCL = 0x80;
125 1 SYNCDELAY;
126 1 // 22/08/2006 ACR mod END: this section belonged (except with different OUT endpoints) to the bulkloop exa
-mple. Let's keep it for now
127 1
128 1 /*
129 1 // 22/08/2006 ACR mod BEGIN: rimuovo questo pezzo di codice che avevo scritto in passato perche' mi sembra
- che la stessa funzione sia ora eseguita dal pezzo di codice precedente
130 1 // Inizializza la pipe dei dati in arrivo sull'endpoint 4 (OUT endpoint), con lo skip dei pacchetti eventu
-almente contenuti nei due buffer dell'endpoint
131 1 OUTPKTEND = 0x84; // Arm both EP2 buffers to “prime the pump”
132 1 SYNCDELAY;
133 1 OUTPKTEND = 0x84;
134 1 SYNCDELAY;
135 1 */
136 1
137 1 /* 01/10/06 ACR BEGIN tolgo questo codice per vedere se funziona il loopback
138 1 // 22/08/2006 ACR mod BEGIN: configure endpoint FIFOs (see page 351 of TRM)
139 1 EP2FIFOCFG = 0x09; // modalita' AUTOIN e bus dati a 16 bit
140 1 SYNCDELAY;
141 1 EP4FIFOCFG = 0x09; // modalita' AUTOIN e bus dati a 16 bit
142 1 SYNCDELAY;
143 1 EP6FIFOCFG = 0x11; // modalita' AUTOOUT e bus dati a 16 bit
144 1 SYNCDELAY;
145 1 EP8FIFOCFG = 0x11; // modalita' AUTOOUT e bus dati a 16 bit
146 1 SYNCDELAY;
147 1
148 1 // EZ-USB automatically commits data in 512-byte chunks ; questa configurazione coincide con quella di def
-ault
149 1 EP2AUTOINLENH = 0x02;
150 1 SYNCDELAY;
151 1 EP2AUTOINLENL = 0x00;
152 1 SYNCDELAY;
153 1 EP4AUTOINLENH = 0x02;
154 1 SYNCDELAY;
155 1 EP4AUTOINLENL = 0x00;
156 1 SYNCDELAY;
157 1 // 22/08/2006 ACR mod END : configure endpoint FIFOs
158 1 01/10/06 ACR END tolgo questo codice per vedere se funziona il loopback */
159 1
160 1 // 22/08/2006 ACR mod BEGIN: change the polarity of the WAKEUP pin
161 1 WAKEUPCS |= 0x10;
162 1 // 22/08/2006 ACR mod END : configure endpoint FIFOs
163 1
164 1 /*
165 1 // 22/08/2006 ACR mod BEGIN removed for EUDRB application
166 1 // removing this code from the bulkloop example does not prevent loop back from working
167 1 // enable dual autopointer feature
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 4
168 1 AUTOPTRSETUP |= 0x01;
169 1 // 22/08/2006 ACR mod END removed for EUDRB application
170 1 */
171 1
172 1 // 22/08/2006 ACR mod: BEGIN adjust the flags meanings
173 1 PINFLAGSAB = 0xDB; // FLAGA = EMPTY FLAG of EP8 FIFO
174 1 // FLAGB = FULL FLAG of EP4 FIFO
175 1 SYNCDELAY;
176 1 PINFLAGSCD = 0xE8; // FLAGC = EMPTY FLAG of EP2 FIFO - 22/08/2006 ACR mod: added this endpoint fl
-ag
177 1 // FLAGD = FULL FLAG of EP6 FIFO - 22/08/2006 ACR mod: added this endpoint flag NB! change the
- definition of this pin in the FPGA
178 1 SYNCDELAY;
179 1 // 22/08/2006 ACR mod: END adjust the flags meanings
180 1
181 1
182 1 // set all slave FIFO interface pins as active low
183 1 FIFOPINPOLAR = 0x00;
184 1 SYNCDELAY;
185 1
186 1 // prepara portA per generare segnale di reset (PA.0) per FPGA e segnale diagnostico (PA.1 = pacchetto ric
-evuto)
187 1 PORTACFG = 0x80; // 21/08/2006 ACR mod: set bit 7 so that Port A pin 7 alternate function is FLAGD (s
-ee page 283 of the EZ-USB TRM document)
188 1 SYNCDELAY;
189 1
190 1 // reset the FPGA con un reset attivo basso
191 1 OEA |= 0x01; // turn on PA0 as output pin
192 1 IOA |= 0x01; // pull PA0 high initially
193 1 IOA &= 0xFE; // bring PA0 low
194 1
195 1 while ( delaycount > 0 )
196 1 {
197 2 delaycount --;
198 2 };
199 1 IOA |= 0x01; // bring PA0 high
200 1 }
201
202
203 void TD_Poll(void) // Called repeatedly while the device is idle
204 {
205 1
206 1 // 22/08/2006 ACR removed this code, which works as loop back, because it is not needed by the EUDRB appli
-cation
207 1 // 22/08/2006 ACR mod: Test BulkLoop with EP2,EP4 of type IN and EP6,EP8 of type OUT BEGIN
208 1 WORD i;
209 1 WORD count;
210 1
211 1 if(!(EP2468STAT & bmEP8EMPTY))
212 1 { // check EP8 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
213 2 if(!(EP2468STAT & bmEP4FULL))
214 2 { // check EP4 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
215 3 APTR1H = MSB( &EP8FIFOBUF );
216 3 APTR1L = LSB( &EP8FIFOBUF );
217 3
218 3 AUTOPTRH2 = MSB( &EP4FIFOBUF );
219 3 AUTOPTRL2 = LSB( &EP4FIFOBUF );
220 3
221 3 count = (EP8BCH << 8) + EP8BCL;
222 3
223 3 // loop EP8OUT buffer data to EP4IN
224 3 for( i = 0x0000; i < count; i++ )
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 5
225 3 {
226 4 // setup to transfer EP8OUT buffer to EP4IN buffer using AUTOPOINTER(s)
227 4 EXTAUTODAT2 = EXTAUTODAT1;
228 4 }
229 3 EP4BCH = EP8BCH;
230 3 SYNCDELAY;
231 3 EP4BCL = EP8BCL; // arm EP4IN
232 3 SYNCDELAY;
233 3 EP8BCL = 0x80; // re(arm) EP8OUT
234 3 }
235 2 }
236 1
237 1 if(!(EP2468STAT & bmEP6EMPTY))
238 1 { // check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
239 2 if(!(EP2468STAT & bmEP2FULL))
240 2 { // check EP2 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
241 3 APTR1H = MSB( &EP6FIFOBUF );
242 3 APTR1L = LSB( &EP6FIFOBUF );
243 3
244 3 AUTOPTRH2 = MSB( &EP2FIFOBUF );
245 3 AUTOPTRL2 = LSB( &EP2FIFOBUF );
246 3
247 3 count = (EP6BCH << 8) + EP6BCL;
248 3
249 3 // loop EP6OUT buffer data to EP2IN
250 3 for( i = 0x0000; i < count; i++ )
251 3 {
252 4 // setup to transfer EP6OUT buffer to EP2IN buffer using AUTOPOINTER(s)
253 4 EXTAUTODAT2 = EXTAUTODAT1;
254 4 }
255 3 EP2BCH = EP6BCH;
256 3 SYNCDELAY;
257 3 EP2BCL = EP6BCL; // arm EP2IN
258 3 SYNCDELAY;
259 3 EP6BCL = 0x80; // re(arm) EP6OUT
260 3 }
261 2 }
262 1 // 22/08/2006 ACR mod: Test BulkLoop with EP2,EP4 of type IN and EP2,EP4 of type OUT BEGIN
263 1
264 1 }
265
266 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
267 {
268 1 return(TRUE);
269 1 }
270
271 BOOL TD_Resume(void) // Called after the device resumes
272 {
273 1 return(TRUE);
274 1 }
275
276 //-----------------------------------------------------------------------------
277 // Device Request hooks
278 // The following hooks are called by the end point 0 device request parser.
279 //-----------------------------------------------------------------------------
280
281 BOOL DR_GetDescriptor(void)
282 {
283 1 return(TRUE);
284 1 }
285
286 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 6
287 {
288 1 Configuration = SETUPDAT[2];
289 1 return(TRUE); // Handled by user code
290 1 }
291
292 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
293 {
294 1 EP0BUF[0] = Configuration;
295 1 EP0BCH = 0;
296 1 EP0BCL = 1;
297 1 return(TRUE); // Handled by user code
298 1 }
299
300 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
301 {
302 1 AlternateSetting = SETUPDAT[2];
303 1 return(TRUE); // Handled by user code
304 1 }
305
306 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
307 {
308 1 EP0BUF[0] = AlternateSetting;
309 1 EP0BCH = 0;
310 1 EP0BCL = 1;
311 1 return(TRUE); // Handled by user code
312 1 }
313
314 BOOL DR_GetStatus(void)
315 {
316 1 return(TRUE);
317 1 }
318
319 BOOL DR_ClearFeature(void)
320 {
321 1 return(TRUE);
322 1 }
323
324 BOOL DR_SetFeature(void)
325 {
326 1 return(TRUE);
327 1 }
328
329 BOOL DR_VendorCmnd(void)
330 {
331 1 BYTE tmp;
332 1
333 1 switch (SETUPDAT[1])
334 1 {
335 2 case VR_NAKALL_ON:
336 2 tmp = FIFORESET;
337 2 tmp |= bmNAKALL;
338 2 SYNCDELAY;
339 2 FIFORESET = tmp;
340 2 break;
341 2 case VR_NAKALL_OFF:
342 2 tmp = FIFORESET;
343 2 tmp &= ~bmNAKALL;
344 2 SYNCDELAY;
345 2 FIFORESET = tmp;
346 2 break;
347 2 default:
348 2 return(TRUE);
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 7
349 2 }
350 1
351 1 return(FALSE);
352 1 }
353
354 //-----------------------------------------------------------------------------
355 // USB Interrupt Handlers
356 // The following functions are called by the USB interrupt jump table.
357 //-----------------------------------------------------------------------------
358
359 // Setup Data Available Interrupt Handler
360 void ISR_Sudav(void) interrupt 0
361 {
362 1 GotSUD = TRUE; // Set flag
363 1 EZUSB_IRQ_CLEAR();
364 1 USBIRQ = bmSUDAV; // Clear SUDAV IRQ
365 1 }
366
367 // Setup Token Interrupt Handler
368 void ISR_Sutok(void) interrupt 0
369 {
370 1 EZUSB_IRQ_CLEAR();
371 1 USBIRQ = bmSUTOK; // Clear SUTOK IRQ
372 1 }
373
374 void ISR_Sof(void) interrupt 0
375 {
376 1 EZUSB_IRQ_CLEAR();
377 1 USBIRQ = bmSOF; // Clear SOF IRQ
378 1 }
379
380 void ISR_Ures(void) interrupt 0
381 {
382 1 // whenever we get a USB reset, we should revert to full speed mode
383 1 pConfigDscr = pFullSpeedConfigDscr;
384 1 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
385 1 pOtherConfigDscr = pHighSpeedConfigDscr;
386 1 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
387 1
388 1 EZUSB_IRQ_CLEAR();
389 1 USBIRQ = bmURES; // Clear URES IRQ
390 1 }
391
392 void ISR_Susp(void) interrupt 0
393 {
394 1 Sleep = TRUE;
395 1 EZUSB_IRQ_CLEAR();
396 1 USBIRQ = bmSUSP;
397 1 }
398
399 void ISR_Highspeed(void) interrupt 0
400 {
401 1 if (EZUSB_HIGHSPEED())
402 1 {
403 2 pConfigDscr = pHighSpeedConfigDscr;
404 2 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
405 2 pOtherConfigDscr = pFullSpeedConfigDscr;
406 2 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
407 2 }
408 1
409 1 EZUSB_IRQ_CLEAR();
410 1 USBIRQ = bmHSGRANT;
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 8
411 1 }
412 void ISR_Ep0ack(void) interrupt 0
413 {
414 1 }
415 void ISR_Stub(void) interrupt 0
416 {
417 1 }
418 void ISR_Ep0in(void) interrupt 0
419 {
420 1 }
421 void ISR_Ep0out(void) interrupt 0
422 {
423 1 }
424 void ISR_Ep1in(void) interrupt 0
425 {
426 1 }
427 void ISR_Ep1out(void) interrupt 0
428 {
429 1 }
430 void ISR_Ep2inout(void) interrupt 0
431 {
432 1 }
433 void ISR_Ep4inout(void) interrupt 0
434 {
435 1 }
436 void ISR_Ep6inout(void) interrupt 0
437 {
438 1 }
439 void ISR_Ep8inout(void) interrupt 0
440 {
441 1 }
442 void ISR_Ibn(void) interrupt 0
443 {
444 1 }
445 void ISR_Ep0pingnak(void) interrupt 0
446 {
447 1 }
448 void ISR_Ep1pingnak(void) interrupt 0
449 {
450 1 }
451 void ISR_Ep2pingnak(void) interrupt 0
452 {
453 1 }
454 void ISR_Ep4pingnak(void) interrupt 0
455 {
456 1 }
457 void ISR_Ep6pingnak(void) interrupt 0
458 {
459 1 }
460 void ISR_Ep8pingnak(void) interrupt 0
461 {
462 1 }
463 void ISR_Errorlimit(void) interrupt 0
464 {
465 1 }
466 void ISR_Ep2piderror(void) interrupt 0
467 {
468 1 }
469 void ISR_Ep4piderror(void) interrupt 0
470 {
471 1 }
472 void ISR_Ep6piderror(void) interrupt 0
C51 COMPILER V7.07 EUDRBLOOPBACK 10/01/2006 14:39:00 PAGE 9
473 {
474 1 }
475 void ISR_Ep8piderror(void) interrupt 0
476 {
477 1 }
478 void ISR_Ep2pflag(void) interrupt 0
479 {
480 1 }
481 void ISR_Ep4pflag(void) interrupt 0
482 {
483 1 }
484 void ISR_Ep6pflag(void) interrupt 0
485 {
486 1 }
487 void ISR_Ep8pflag(void) interrupt 0
488 {
489 1 }
490 void ISR_Ep2eflag(void) interrupt 0
491 {
492 1 }
493 void ISR_Ep4eflag(void) interrupt 0
494 {
495 1 }
496 void ISR_Ep6eflag(void) interrupt 0
497 {
498 1 }
499 void ISR_Ep8eflag(void) interrupt 0
500 {
501 1 }
502 void ISR_Ep2fflag(void) interrupt 0
503 {
504 1 }
505 void ISR_Ep4fflag(void) interrupt 0
506 {
507 1 }
508 void ISR_Ep6fflag(void) interrupt 0
509 {
510 1 }
511 void ISR_Ep8fflag(void) interrupt 0
512 {
513 1 }
514 void ISR_GpifComplete(void) interrupt 0
515 {
516 1 }
517 void ISR_GpifWaveform(void) interrupt 0
518 {
519 1 }
520
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 756 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 2 4
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)